Conventional approaches for enabling sense amplifiers generally involve turning ON a sense amplifier after an address transition detection has occurred, waiting a predetermined time and then turning OFF the sense amplifier. The predetermined time is generally a fixed delay, which must be designed prior to fabrication of the device and must accommodate voltage, temperature and process variations. The delay is generally longer than required in order to provide enough margin for proper operation of the sense amplifier under worst case conditions. As a result, the sense amplifier may be left ON for a longer time than is necessary.
Referring to FIG. 1 a circuit 10 is shown implementing a sense amplifier in the context of a memory array. The circuit 10 comprises an address path block 12, a memory array block 14, a sense amplifier block 16, an output path block 18, an address transition detection block 20 and a control block 22. The address path block 12 and the address transition detection block 20 each receive an external address signal. The address transition detection block 20 presents an address transition detect signal (ATD) to the control block 22. The control block 22 presents a signal WL.sub.-- ENABLE to the address path block 12. The address path block 12 presents a signal WL to the memory array block 14. The memory array block 14 presents a signal WL.sub.-- DETECT to the control block 22 as well as a signal TBUS to the sense amplifier block 16. The sense amplifier block 16 presents a signal SA.sub.-- OUT to the output path block 18. The output path block 18 presents a signal OUTPUT representing data read from the memory array block 14. The control block 22 presents a signal SA.sub.-- ENABLE to the sense amplifier block 16 that is a fixed width pulsed delay. The pulsed delay is a fixed delay based on the worst case conditions allowing enough time for the sense amplifier block 16 to properly sense the signals received from the memory array block 14. The sense amplifier block 16 can comprise a number of sense amplifiers that may each be controlled by the pulsed delay presented by the control block 22. Since a number of sense amplifiers can be controlled by the same signal SA.sub.-- ENABLE, the length of the pulsed delay is generally increased to ensure proper margin for sensing of the slowest sense amplifier.
Referring to FIG. 2, a timing diagram illustrating the various signals of FIG. 1 is shown. The address signals presented to the address path block 12 and the address transition detection block 20 are shown having a transition 30. The signal ATD presents a pulse 32 in response to an external address transition. The signal WL.sub.-- ENABLE has a positive transition 34 that responds to the pulse 32 of the signal ATD. The signal WL.sub.-- ENABLE generally remains high until the end of the signal SA.sub.-- ENABLE. The signal WL responds to the transition of the signal WL.sub.-- ENABLE by adding a positive transition 36. The signal WL remains high as long as the signal WL.sub.-- ENABLE remains high. The signal WL.sub.-- DETECT has a positive transition 38 that responds to the positive transition 36 of the signal WL. The signal SA.sub.-- ENABLE has a positive transition 42 that responds to the positive transition 38 of the signal WL.sub.-- DETECT. The signal TBUS has a transition 39 that also responds to the positive transition 36 of the signal WL. The signal SA.sub.-- OUT has a transition 40 that responds to the positive transition 42 of the signal SA.sub.-- ENABLE and indicates the sense amplifiers have evaluated the contents of the memory array block 14.
The signal SA.sub.-- ENABLE generally remains high for a fixed delay indicated as "pulsed delay". During the pulsed delay, the sense amplifier begins sensing of the signals received from the memory array block 14. The beginning of this sensing is indicated by the vertical line 44. The vertical line 46 indicates the end of the actual time the sense amplifiers are sensing, which is indicated by the transition 40. The time between the vertical line 44 and the vertical line 46 represents a portion of the pulsed delay where the sense amplifiers are actually sensing the signal. The pulsed delay has a negative transition 48 that occurs after the fixed and predetermined delay. A vertical line 50 represents a time when the sense amplifiers actually turn OFF. The time between the vertical line 46 and the vertical line 50 represents a time when the sense amplifiers are active, but do not provide any meaningful function, since the outputs have already changed at the transition 40. During this unproductive time, the sense amplifiers continue to use unneeded current, which is generally undesirable. The signal WL.sub.-- ENABLE has a negative transition 52 that responds to the negative transition 48 of the signal SA.sub.-- ENABLE. The signal SA.sub.-- OUT has a transition 53 that responds to the negative transition 48. The signal WL has a negative transition 54 that responds to the negative transition 52 of the signal WL.sub.-- ENABLE. The signal WL.sub.-- DETECT has a negative transition 56 that responds to the negative transition 54 of the signal WL. The signal TBUS has a transition 57 that responds to the transition 54 of the signal WL. The signal OUTPUT has a transition 59 that responds to the end of the sense amplifier at the vertical line 46.
Referring to FIG. 3, a block diagram of the control block 22 is shown. The signal WL.sub.-- DETECT is presented to a pulsed delay block 60 that presents the signal SA.sub.-- ENABLE. The pulse generator block 62 responds to a negative transition of the signal SA.sub.-- ENABLE and presents a pulse to a reset input of an SR latch 64. The signal ATD is presented to the set input of the SR latch 64. The Q output of the SR latch 64 presents the signal WL.sub.-- ENABLE.
Referring to FIG. 4, the pulsed delay block 60 is shown in greater detail comprising a number of inverters 66a-66n and a gate 68. The amount of delay generally depends on a number of inverters 66a-66n. FIG. 5 illustrates a more detailed diagram of the pulse generator block 62 comprising a number of inverters 70a-70n and a gate 72. Similar to the pulsed delay block 60, the number of inverters 70a-70n generally controls the amount of delay at the output. The type of gate (i.e., the gate 68 or the gate 72) generally controls whether the delayed pulse is a positive or negative edge triggered device. Since the pulsed delay block 60 has an AND gate, a positive edge-triggered device results. Similarly, since the pulse generator block 62 has a NOR gate 72, a negative edge-triggered device results.
Since both the pulsed delay block 60 and the pulse generator block 62 each comprise a number of inverters 66a-66n and 70a-70n, used as delay elements, the amount of delay presented by the signal SA.sub.-- ENABLE is a predetermined delay, with the inherent disadvantages discussed previously.